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? semiconductor components industries, llc, 2010 april, 2010 ? rev. 7 1 publication order number: ncp3163/d ncp3163, ncv3163 3.4 a, step-up/down/ inverting 50-300 khz switching regulator the ncp3163 series is a performance enhancement to the popular mc33163 and mc34163 monolithic dc ? dc converters. these devices consist of an internal temperature compensated reference, comparator, controlled duty cycle oscillator with an active current limit circuit, driver and high current output switch. this controller was specifically designed to be incorporated in step ? down, step ? up, or voltage ? inverting applications with a minimum number of external components. the ncp3163 comes in an exposed pad package which can greatly increase the power dissipation of the built in power switch. features ? output switch current in excess of 3.0 a ? 3.4 a peak switch current ? frequency is adjustable from 50 khz to 300 khz ? operation from 2.5 v to 40 v input ? externally adjustable operating frequency ? precision 2% reference for accurate output voltage control ? driver with bootstrap capability for increased efficiency ? cycle ? by ? cycle current limiting ? internal thermal shutdown protection ? low voltage indicator output for direct microprocessor interface ? exposed pad power package ? low standby current ? ncv prefix for automotive and other applications requiring site and change control ? these are pb ? free devices + 16 9 10 11 12 13 14 15 8 7 6 5 4 3 2 lvi oscillator + + - current limit figure 1. typical buck application circuit (bottom view) - + + + - 1 v cc v cc v cc v in c in thermal v out + c o r s q see detailed ordering and shipping information in the package dimensions section on page 18 of this data sheet. ordering information marking diagrams ncx3163y = specific device code x = p or v y = blank or b a = assembly location wl = wafer lot yy = year ww = work week g or = pb ? free package 1 16 soic ? 16w exposed pad pw suffix case 751ag http://onsemi.com 16 1 ncx3163ypw awlyywwg *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 18 ? lead dfn mn suffix case 505 1 ncx3163y awlyyww 11 8 18 (note: microdot may be in either location)
ncp3163, ncv3163 http://onsemi.com 2 16 9 10 11 12 13 14 15 8 7 6 5 4 3 2 lvi oscillator + + - current limit figure 2. representative block diagram (bottom view) - + + + - 1 v cc v cc v cc thermal r s q driver collector switch collector 0.25 v switch emitter bootstrap input voltage feedback 1 voltage feedback 2 lvi output gnd i pksense v cc r sc timing capacitor 2.0 ma 7.0 v 60 q1 q2 1.125 v 15 k 1.25 v feedback comparator shutdown c t r dt 45 k latch + - = sink only positive true logic pin function description soic16 dfn18 pin name description 1 15 lvi output this pin will sink current when fb1 and fb2 are less than the lvi threshold (v th ). 2 16 voltage feedback 2 connecting this pin to a resistor divider off of the output will regulate the application according to the v out design equation in figure 22. 3 17 voltage feedback 1 connecting this pin directly to the output will regulate the device to 5.05 v. 4 18 gnd ground pin for all internal circuits and power switch. 6 1 timing capacitor connect a capacitor to this pin to set the frequency. the addition of a parallel resist- or will decrease the maximum duty cycle and increase the frequency. 7 3 v cc power pin for the ic. 8 4 i pk sense when (v cc ? v ipksense ) > 250 mv the circuit resets the output driver on a pulse by pulse basis. 9 5 drive collector voltage driver collector 10,11 6,7,8,9 switch collector internal switch transistor collector 14,15 10,11,12,13 switch emitter internal switch transistor emitter 16 14 bootstrap input connect this pin to v cc for operation at low v cc levels. for some topologies, a series resistor and capacitor can be utilized to improve the converter efficiency. 5,12,13 2 no connect these pins have no connection. exposed pad exposed pad exposed pad the exposed pad beneath the package must be connected to gnd (pin 4). addi- tionally, using proper layout techniques, the exposed pad can greatly enhance the power dissipation capabilities of the ncp3163.
ncp3163, ncv3163 http://onsemi.com 3 maximum ratings (note 1) rating symbol value unit power supply voltage v cc 0 to +40 v switch collector voltage range v csw ? 1.0 to +40 v switch emitter voltage range v esw ? 2.0 to +40 v switch collector to emitter voltage v cesw +40 v switch current i sw 3.4 a driver collector voltage (pin 8) v cc ? 1.0 to +40 v driver collector current (pin 8) i cc 150 ma bootstrap input current range i bst ? 100 to +100 ma current sense input voltage range v ipksns (v cc ? 7.0) to (v cc + 1.0) v feedback and timing capacitor input voltage range v in ? 1.0 to +7.0 v low voltage indicator output voltage range v clvi ? 1.0 to +40 v low voltage indicator output sink current i clvi 10 ma power dissipation and thermal characteristics thermal characteristics thermal resistance, junction ? to ? case thermal resistance, junction ? to ? air r jc r ja 15 56 c/w storage temperature range t stg ? 65 to +150 c maximum junction temperature t jmax +150 c operating ambient temperature (note 3) ncp3163 ncp3163b ncv3163 t a 0 to +70 ? 40 to +85 ? 40 to +125 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and exceeds the following tests: human body model 2000 v per mil ? std ? 883, method 3015. machine model method 200 v. charged device model 750 v for corner pins and 500 v for others (according to aec ? q100). 2. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78. 3. maximum package power dissipation limits must be observed. maximum junction temperature must not be exceeded. 4. the pins which are not defined may not be loaded by external signals. 116 15 14 13 12 11 10 9 2 3 4 5 6 7 8 (top view) lvi output voltage feedback 2 voltage feedback 1 gnd timing capacitor v cc i pk sense bootstrap input switch emitter n/c switch collector driver collector pin connections n/c gnd voltage feedback 1 lvi output bootstrap input switch emitter switch emitter switch emitter switch emitter voltage feedback 2 timing capacitor n/c v cc i pk sense switch collector switch collector switch collector switch collector driver collector 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 17 18 note: pin 18 must be tied to ep flag on pcb gnd ep flag
ncp3163, ncv3163 http://onsemi.com 4 electrical characteristics (v cc = 15 v, pin 16 = v cc , c t = 270 pf, r t = 15 k , for typical values t a = 25 c, for min/max values t a is the operating ambient temperature range that applies (note 7), unless otherwise noted.) characteristic symbol min typ max unit oscillator frequency t a = 25 c, v cc = 15 v total variation over v cc = 2.5 v to 40 v and temperature f osc 225 212 250 250 275 288 khz charge current i chg ? 225 ? a discharge current i dischg ? 25 ? a charge to discharge current ratio ncp3163 ncv3163 i chg /i dischg 8.0 7.0 9.0 9.0 10.5 10.5 ? sawtooth peak voltage v osc(p) ? 1.25 ? v sawtooth valley voltage v osc(v) ? 0.55 ? v feedback comparator 1 threshold voltage t a = 25 c total variation over v cc = 2.5 v to 40 v and temperature v th(fb1) 4.9 4.85 5.05 ? 5.2 5.25 v threshold voltage ? line regulation (v cc = 2.5 v to 40 v, t a = 25 c) regline (fb1) ? 0.008 0.03 %/v input bias current (v fb1 = 5.05 v) i ib(fb1) ? 100 200 a feedback comparator 2 threshold voltage t a = 25 c, v cc = 15 v total variation over v cc = 2.5 v to 40 v and temperature v th(fb2) 1.225 1.213 1.25 ? 1.275 1.287 v threshold voltage ? line regulation (v cc = 2.5 v to 40 v, t a = 25 c) regline (fb1) ? 0.008 0.03 %/v input bias current (v fb2 = 1.25 v) i ib(fb2) ? 0.4 ? 0.4 a current limit comparator threshold voltage t a = 25 c total variation over v cc = 2.5 v to 40 v, and temperature v th(sense) ? 225 250 ? ? 270 mv input bias current (v ipk (sense) = 15 v) i ib(sense) ? 1.0 20 a driver and output switch (note 6) saturation voltage (i sw = 2.5 a, pins 14, 15 grounded) non ? darlington (r pin 9 = 110 to v cc , i sw /i drv 20) ncp3163 ncv3163 darlington connection (pins 9, 10, 11 connected) ncp3163 ncv3163 v ce(sat) ? ? ? ? 0.6 0.6 1.0 1.0 1.0 1.5 1.4 1.5 v collector off ? state leakage current (v ce = 40 v) i c(off) ? 0.02 100 a bootstrap input current source (v bs = v cc + 5.0 v) i source(drv) 0.5 2.0 4.0 ma bootstrap input zener clamp voltage (i z = 25 ma) v z v cc + 6.0 v cc + 7.0 v cc + 9.0 v low voltage indicator input threshold (v fb2 increasing) v th 1.07 1.125 1.18 v input hysteresis (v fb2 decreasing) v h ? 15 ? mv output sink saturation voltage (i sink = 2.0 ma) v ol(lvi) ? 0.15 0.4 v output off ? state leakage current (v oh = 15 v) i oh ? 0.01 5.0 a total device standby supply current (v cc = 2.5 v to 40 v, pin 8 = v cc , pins 6, 14, 15 = gnd, remaining pins open) i cc ? 6.0 10 ma 5. maximum package power dissipation limits must be observed. 6. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 7. t low =0 c for ncp3163 t high =+70 c for ncp3163 = ? 40 c for ncp3163b = + 85 c for ncp3163b = ? 40 c for ncv3163 = + 125 c for ncv3163
ncp3163, ncv3163 http://onsemi.com 5 figure 3. oscillator frequency vs. timer capacitance (c t ) 300 0 c t , timer capacitance (pf) frequency (khz) 200 100 50 100 200 300 400 500 600 700 v cc = 15 v t a = 25 c figure 4. oscillator frequency change vs. temperature when only c t is connected to pin 6 2.0 -55 t a , ambient temperature ( c) f osc , oscillator frequency change (%) 0 -2.0 -4.0 -6.0 -25 0 25 50 75 100 125 v cc = 15 v c t = 620 pf figure 5. oscillator frequency change vs. temperature when c t and r t are connected to pin 6 4.0 -50 temperature ( c) f osc , oscillator frequency change (%) 0 -2.0 -8.0 -10 -25 0 25 50 75 100 125 -6.0 -4.0 2.0 v cc = 15 v c t = 230 pf r t = 20 k 150 250 r t = 15 k r t = open figure 6. feedback comparator 1 input bias current vs. temperature figure 7. feedback comparator 2 threshold voltage vs. temperature i ib , input bias current (a) 140 -55 t a , ambient temperature ( c) 120 100 80 60 -25 0 25 50 75 100 125 v th(fb2) , comparator 2 threshold voltage (mv) 1300 1280 1260 1240 1220 1200 -55 t a , ambient temperature ( c) -25 0 25 50 75 100 125 v th typ = 1250 mv v th min = 1225 mv v cc = 15 v v fb1 = 5.05 v v th max = 1275 mv v cc = 15 v
ncp3163, ncv3163 http://onsemi.com 6 2.8 2.4 2.0 1.6 1.2 -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c) i source (drv) , bootstrap input current source (ma ) v cc = 15 v pin 16 = v cc + 5.0 v v z 7.6 7.4 7.2 7.0 6.8 -55 -25 0 25 50 75 100 12 5 t a , ambient temperature ( c) i z = 25 ma , bootstrap input zener clamp voltage (v ) figure 8. bootstrap input current source vs. temperature figure 9. bootstrap input zener clamp voltage vs. temperature v ce (sat) 0 -0.4 0 0.8 2.4 3.2 i e , emitter current (a) , source saturation (v) -0.8 -1.2 -1.6 -2.0 1.2 1.0 i c , collector current (a) 0.8 0.6 0.4 0.2 0 gnd v ce (sat) , sink saturation (v) 1.6 bootstrapped, pin 16 = v cc + 5.0 v non-bootstrapped, pin 16 = v cc v cc 0 0.8 2.4 3.2 1.6 figure 10. output switch source saturation vs. emitter current figure 11. output switch sink saturation vs. collector current darlington, pins 9, 10, 11 connected grounded emitter configuration collector sinking current from v cc pins 7, 8 = v cc = 15 v pins 4, 5, 12, 13, 14, 15 = gnd t a = 25 c, (note 2) saturated switch, r pin9 = 110 to v cc darlington configuration emitter sourcing current to gnd pins 7, 8, 10, 11 = v cc pins 4, 5, 12, 13 = gnd t a = 25 c, (note 2) figure 12. output switch negative emitter voltage vs. temperature figure 13. low voltage indicator output sink saturation voltage vs. sink current v e , emitter voltage (v) 0 -0.4 -0.8 -1.2 -1.6 -2.0 -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c) i c = 10 ma v ol (lvi) , output saturation voltage (v) 0.5 0.4 0 2.0 4.0 6.0 8.0 i sink , output sink current (ma) 0.3 0.2 0.1 0 v cc =5 v t a =25 c gnd i c = 10 a v cc = 15 v pins 7, 8, 9, 10, 16 = v cc pins 4, 6 = gnd pin 14 driven negative
ncp3163, ncv3163 http://onsemi.com 7 figure 14. current limit comparator threshold voltage vs. temperature figure 15. current limit comparator input bias current vs. temperature v th (ipk sense) , threshold voltage (mv ) 254 252 250 248 246 -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c) i ib (sense) input bias current ( a) 1.6 1.4 1.2 1.0 0.8 -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c) 0.6 , v cc = 15 v v cc = 15 v v ipk (sense) = 15 v i cc , supply current (ma) figure 16. standby supply current vs. supply voltage figure 17. standby supply current vs. temperature i cc , supply current (ma) 8.0 6.0 4.0 2.0 0 0 10203040 v cc , supply voltage (v) pins 7, 8, 16 = v cc pins 4, 6, 14 = gnd remaining pins open t a = 25 c 7.2 6.4 5.6 4.8 -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c) 4.0 v cc = 15 v pins 7, 8, 16 = v cc pins 4, 6, 14 = gnd remaining pins open figure 18. minimum operating supply voltage vs. temperature 3.0 2.6 2.2 1.8 1.4 1.0 -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c) v cc(min) , minimum operating supply voltage (v) pin 16 open c t = 620 pf pins 7,8 = v cc pins 4, 14 = gnd pin 9 = 1.0 k to 15 v pin 10 = 100 to 15 v pin 16 = v cc
ncp3163, ncv3163 http://onsemi.com 8 introduction the ncp3163 is a monolithic power switching regulator optimized for dc ? to ? dc converter applications. the combination of its features enables the system designer to directly implement step ? up, step ? down, and voltage ? inverting converters with a minimum number of external components. potential applications include cost sensitive consumer products as well as equipment for the automotive, computer, and industrial markets. a representative block diagram is shown in figure 2. operating description the ncp3163 operates as a fixed on ? time, variable off ? time voltage mode ripple regulator. in general, this mode of operation is somewhat analogous to a capacitor charge pump and does not require dominant pole loop compensation for converter stability. the t ypical operating waveforms are shown in figure 19. the output voltage waveform shown is for a step ? down converter with the ripple and phasing exaggerated for clarity. during initial converter startup, the feedback comparator senses that the output voltage level is below nominal. this causes the output switch to turn on and off at a frequency and duty cycle controlled by the oscillator, thus pumping up the output filter capacitor. when the output voltage level reaches nominal, the feedback comparator sets the latch, immediately terminating switch conduction. the feedback comparator will inhibit the switch until the load current causes the output voltage to fall below nominal. under these conditions, output switch conduction can be inhibited for a partial oscillator cycle, a partial cycle plus a complete cycle, multiple cycles, or a partial cycle plus multiple cycles. oscillator the oscillator frequency and on ? time of the output switch are programmed by the value selected for timing capacitor c t . capacitor c t is charged and dischar ged by a 9 to 1 ratio internal current source and sink, generating a negative going sawtooth waveform at pin 6. as c t charges, an internal pulse is generated at the oscillator output. this pulse is connected to the nor gate center input, preventing output switch conduction, and to the and gate upper input, allowing the latch to be reset if the comparator output is low. thus, the output switch is always disabled during ramp ? up and can be enabled by the comparator output only at the start of ramp ? down. the oscillator peak and valley thresholds are 1.25 v and 0.55 v, respectively, with a charge current of 225 a and a discharge current of 25 a, yielding a maximum on ? time duty cycle of 90%. a reduction of the maximum duty cycle may be required for specific converter configurations. this can be accomplished with the addition of an external deadtime resistor (r dt ) placed across c t . the resistor increases the discharge current which reduces the on ? time of the output switch. the converter output can be inhibited by clamping c t to ground with an external npn small ? signal transistor. to calculate the frequency when only c t is connected to pin 6, use the equations found in figure 22. when r t is also used, the frequency and maximum duty cycle can be calculated with the ncp3163 design tool found at www.onsemi.com. comparator output timing capacitor c t oscillator output output switch output voltage nominal output voltage level 1 0 1.25 v 0.55 v 1 0 on off figure 19. typical operating waveforms startup quiescent operation 9t t
ncp3163, ncv3163 http://onsemi.com 9 feedback and low voltage indicator comparators output voltage control is established by the feedback comparator. the inverting input is internally biased at 1.25 v and is not pinned out. the converter output voltage is typically divided down with two external resistors and monitored by the high impedance noninverting input at pin 2. the maximum input bias current is 0.4 a, which can cause an output voltage error that is equal to the product of the input bias current and the upper divider resistance value. for applications that require 5.0 v, the converter output can be directly connected to the noninverting input at pin 3. the high impedance input, pin 2, must be grounded to prevent noise pickup. the internal resistor divider is set for a nominal voltage of 5.05 v. the additional 50 mv compensates for a 1.0% voltage drop in the cable and connector from the converter output to the load. the feedback comparator?s output state is controlled by the highest voltage applied to either of the two noninverting inputs. the low v oltage indicator (lvi) comparator is designed for use as a reset controller in microprocessor ? based systems. the inverting input is internally biased at 1.125 v, which sets the noninverting input thresholds to 90% of nominal. the lvi comparator has 15 mv of hysteresis to prevent erratic reset operation. the open collector output is capable of sinking in excess of 6.0 ma (see figure 13). an external resistor (r lvi ) and capacitor (c dly ) can be used to program a reset delay time (t dly ) by the formula shown below, where v th(mpu) is the microprocessor reset input threshold. refer to figure 20. t dly = r lvi ? c dly ? in 1 1 ? v th(mpu) v out figure 20. partial application schematic showing implementation of lvi delay with r lvi and c dly l lvi 1 + + - 3 2 (bottom view) + + - 16 14 15 1.125 v 1.25 v feedback comparator c o v out low voltage indicator output c dly r lvi current limit comparator, latch and thermal shutdown with a voltage mode ripple converter operating under normal conditions, output switch conduction is initiated by the oscillator and terminated by the voltage feedback comparator. abnormal operating conditions occur when the converter output is overloaded or when feedback voltage sensing is lost. under these conditions, the current limit comparator will protect the output switch. the switch current is converted to a voltage by inserting a fractional ohm resistor, r sc , in series with v cc and output switch transistor q 2 . the voltage drop across r sc is monitored by the current sense comparator. if the voltage drop exceeds 250 mv with respect to v cc , the comparator will set the latch and terminate output switch conduction on a cycle ? by ? cycle basis. this comparator/latch configuration ensures that the output switch has only a single on ? time during a given oscillator cycle. the calculation for a value of r sc is: r sc 0.25 v i pk (switch) figures 14 and 15 show that the current sense comparator threshold is tightly controlled over temperature and has a typical input bias current of 1.0 a. the propagation delay from the comparator input to the output switch is typically 200 ns. the parasitic inductance associated with r sc and the circuit layout should be minimized. this will prevent unwanted voltage spikes that may falsely trip the current limit comparator. internal thermal shutdown circuitry is provided to protect the ic in the event that the maximum junction temperature is exceeded. when activated, typically at 170 c, the latch is forced into the ?set? state, disabling the output switch. this feature is provided to prevent catastrophic failures from accidental device overheating. it is not intended to be used as a replacement for proper heatsinking. driver and output switch to aid in system design flexibility and conversion efficiency, the driver current source and collector, and output switch collector and emitter are pinned out separately. this allows the designer the option of driving the output switch into saturation with a selected force gain or driving it near saturation when connected as a darlington. the output switch has a typical current gain of 70 at 2.5 a and is designed to switch a maximum of 40 v collector to emitter, with up to 3.4 a peak collector current. the minimum value for r sc is: r sc(min) 0.25 v 3.4 a 0.0735
ncp3163, ncv3163 http://onsemi.com 10 when configured for step ? down or voltage ? inverting applications (see application notes at the end of this document) the inductor will forward bias the output rectifier when the switch turns off. rectifiers with a high forward voltage drop or long turn ? on delay time should not be used. if the emitter is allowed to go sufficiently negative, collector current will flow, causing additional device heating and reduced conversion efficiency. figure 12 shows that by clamping the emitter to 0.5 v, the collector current will be in the range 10 a over temperature. a 1n5822 or equivalent schottky barrier rectifier is recommended to fulfill these requirements. a bootstrap input is provided to reduce the output switch saturation voltage in step ? down and voltage ? inverting converter applications. this input is connected through a series resistor and capacitor to the switch emitter and is used to raise the internal 2.0 ma bias current source above v cc . an internal zener limits the bootstrap input voltage to v cc +7.0 v. the capacitor?s equivalent series resistance must limit the zener current to less than 100 ma. an additional series resistor may be required when using tantalum or other low esr capacitors. the equation below is used to calculate a minimum value bootstrap capacitor based on a minimum zener voltage and an upper limit current source. c b(min) i t v 4.0 ma t on 4.0 v 0.001 t on parametric operation of the ncp3163 is guaranteed over a supply voltage range of 2.5 v to 40 v. when operating below 3.0 v, the bootstrap input should be connected to v cc . figure 18 shows that functional operation down to 1.7 v at room temperature is possible. package the ncp3163 is contained in a heatsinkable 16 ? lead plastic package in which the die is mounted on a special heat tab copper alloy pad. this pad is designed to be soldered directly to a gnd connection on the printed circuit board to improve thermal conduction. since this pad directly contacts the substrate of the die, it is important that this pad be always soldered to gnd, even if surface mount heat sinking is not being used. figure 21 shows recommended layout techniques for this package. figure 21. layout guidelines to obtain maximum package power dissipation flare metal for maximum heat sinking 0.145 0.175 exposed pad 0.188 vias to 2nd layer metal for maximum heat sinking minimum recommended exposed copper applications figures 23 through 30 show the simplicity and flexibility of the ncp3163. three main converter topologies are demonstrated with actual test data shown below each of the circuit diagrams. figure 22 gives the relevant design equations for the key parameters. additionally, a complete application design aid for the ncp3163 can be found at www.onsemi.com.
ncp3163, ncv3163 http://onsemi.com 11 calculation step ? down step ? up voltage ? inverting t on t off (see notes 1,2,3) v out v f v in v sat v out v out v f v in v in v sat |v out | v f v in v sat t on ? t on t off t on t off 1 ? t on t off t on t off 1 ? t on t off t on t off 1 c t 32.143 10 6 f 20 10 12 32.143 10 6 f 20 10 12 32.143 10 6 f 20 10 12 i l(avg) i out i out t on t off 1 i out t on t off 1 i pk (switch) i l(avg) i l 2 i l(avg) i l 2 i l(avg) i l 2 r sc 0.25 i pk (switch) 0.25 i pk (switch) 0.25 i pk (switch) l v in v sat v out i l t on v in v sat i l t on v in v sat i l t on v ripple(pp) ? i l 1 8c o 2 (esr) 2 t on i out c o t on i out c o v out v ref r 2 r 1 1 v ref r 2 r 1 1 v ref r 2 r 1 1 v in ? v out ? i out ? i l ? ? v ripple(pp) ? nominal operating input voltage. desired output voltage. desired output current. desired peak ? to ? peak inductor ripple current. for maximum output current it is suggested that i l be chosen to be less than 10% of the average inductor current i l(avg) . this will help prevent i pk (switch) from reaching the current limit threshold set by r sc . if the design goal is to use a minimum inductance value, let i l = 2(i l(avg) ). this will proportionally reduce converter output current capability. maximum output switch frequency. desired peak ? to ? peak output ripple voltage. for best performance the ripple voltage should be kept to a low value since it will directly affect line and load regulation. capacitor c o should be a low equivalent series resistance (esr) electrolytic designed for switching regulator applications. the following converter characteristics must be chosen: notes: 1. v sat ? saturation voltage of the output switch, refer to figures 10 and 11. notes: 2. v f ? output rectifier forward voltage drop. typical value for 1n5822 schottky barrier rectifier is 0.5 v. notes: 3. the calculated t on /t off must not exceed the minimum guaranteed oscillator charge to discharge ratio of 8, at the minimum notes: 3. operating input voltage. figure 22. design equations
ncp3163, ncv3163 http://onsemi.com 12 r b l d lvi 1 + + - current limit 8 7 6 5 4 3 2 (bottom view) + + - 16 9 10 11 12 13 14 15 0.25 v r sc v in c t 1.125 v 15 k 1.25 v 45 k feedback comparator q 1 q 2 60 c in c o c b v out - + thermal oscillator r s q latch 2.0 ma 7.0 v figure 23. typical buck application schematic v cc v cc v cc r 1 r 2 r t value of components name value l 47 h d 2 a, 40 v schottky rectifier c in 47 f, 35 v c out 100 f, 10 v c t 270 pf 10% r t 15 k name value r 1 15 k r 2 24.9 k r sc 80 m , 1 w c b 4.7 nf r b 200 test results for v out = 3.3 v test condition results line regulation v in = 8.0 v to 24 v, i out = 2.5 a 13 mv load regulation v in = 12 v, i out = 0 to 2.5 a 25 mv output ripple v in = 12 v, i out = 0 to 2.5 a 100 mvpp efficiency v in = 12 v, i out = 2.5 a 70.3% short circuit current v in = 12 v, r l = 0.1 3.1 a test results for v out = 5.05 v test condition results line regulation v in = 10.2 v to 24 v, i out = 2.5 a 54 mv load regulation v in = 12 v, i out = 0 to 2.5 a 28 mv output ripple v in = 12 v, i out = 0 to 2.5 a 150 mvpp efficiency v in = 12 v, i out = 2.5 a 75.5% short circuit current v in = 12 v, r l = 0.1 3.1 a
ncp3163, ncv3163 http://onsemi.com 13 figure 24. buck layout application specific characteristics figure 25. efficiency vs. output current for the buck demo board at v in = 12 v, t a = 25 c i out (a) efficiency (%) 2.5 2.0 1.5 1.0 0.5 0 50 55 60 65 70 75 80 85 3.3 v eff 5.0 v eff
ncp3163, ncv3163 http://onsemi.com 14 lvi 1 + + - current limit 8 7 6 5 4 3 2 (bottom view) + + - 16 9 10 11 12 13 14 15 0.25 v r sc v in c t 1.125 v 15 k 1.25 v 45 k feedback comparator q 1 q 2 60 c in c o v out + d r 1 r 2 - + thermal oscillator r s q latch 2.0 ma 7.0 v + l figure 26. typical boost application schematic v cc v cc v cc r t value of components for v out = 24 v name value l 33 h d 2 a, 40 v schottky rectifier c in 330 f, 35 v c t 270 pf 10% r t 15 k name value r 1 42.2 k r 2 2.32 k c out 330 f, 25 v r sc 80 m , 1 w test results for v out = 24 v test condition results line regulation v in = 10 v to 20 v, i out = 700 ma 90 mv load regulation v in = 12 v, i out = 0 to 700 ma 80 mv output ripple v in = 12 v, i out = 0 to 700 ma 300 mvpp efficiency v in = 12 v, i out = 700 ma 83% short circuit current v in = 12 v, r l = 0.1 3.1 a
ncp3163, ncv3163 http://onsemi.com 15 figure 27. boost demo board layout figure 28. efficiency vs. output current for the boost demo board at v in = 12 v, t a = 25 c i out (a) efficiency (%) 0.7 0.5 0.4 0.3 0.2 0.1 74 76 78 80 82 84 86 0.6
ncp3163, ncv3163 http://onsemi.com 16 l lvi 1 + + - current limit 8 7 6 5 4 3 2 (bottom view) + + - 16 9 10 11 12 13 14 15 0.25 v r sc v in c t 1.125 v 15 k 1.25 v 45 k feedback comparator q 1 q 2 60 c in c o v out + d r 1 r 2 r b - + thermal oscillator r s q latch 2.0 ma 7.0 v + c b figure 29. typical voltage inverting application schematic r t v cc v cc v cc value of components for v out = ? 15 v name value l 47 h d 2 a, 40 v schottky rectifier c in 270 f, 16 v c out 2 x 270 f, 16 v c t 150 pf 10% name value r 1 1.07 k r 2 11.8 k r sc 80 m , 1 w c b 4.7 nf r b 200 test results for v out = ? 15 v test condition results line regulation v in = 7.0 v to 16 v, i out = 500 ma 35 mv load regulation v in = 12 v, i out = 0 to 500 ma 20 mv output ripple v in = 12 v, i out = 0 to 500 ma 100 mvpp efficiency v in = 12 v, i out = 500 ma 68% short circuit current v in = 12 v, r l = 0.1 3.1 a
ncp3163, ncv3163 http://onsemi.com 17 figure 30. voltage inverting demo board layout figure 31. efficiency vs. output current for the voltage inverting demo board at v in = 12 v, t a = 25 c i out (a) efficiency (%) 0.35 0.3 0.25 0.2 0.15 0.1 50 54 58 62 66 70 0.5 0.45 0.4
ncp3163, ncv3163 http://onsemi.com 18 ordering information device package shipping ? ncp3163pwg soic ? 16 w exposed pad (pb ? free) 47 units / rail ncp3163pwr2g soic ? 16 w exposed pad (pb ? free) 1000 / tape & reel ncp3163bpwg soic ? 16 w exposed pad (pb ? free) 47 units / rail ncp3163bpwr2g soic ? 16 w exposed pad (pb ? free) 1000 / tape & reel ncp3163mnr2g dfn18 (pb ? free) 2500 / tape & reel ncp3163bmnr2g dfn18 (pb ? free) 2500 / tape & reel ncv3163pwg soic ? 16 w exposed pad (pb ? free) 47 units / rail ncv3163pwr2g soic ? 16 w exposed pad (pb ? free) 1000 / tape & reel NCV3163MNR2G dfn18 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp3163, ncv3163 http://onsemi.com 19 package dimensions soic 16 lead wide body, exposed pad pw suffix case 751ag ? 01 issue a g ? w ? ? u ? p m 0.25 (0.010) w ? t ? seating plane k d 16 pl c m 0.25 (0.010) t uw s s m f detail e detail e r x 45 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable protrusion shall be 0.13 (0.005) total in excess of the d dimension at maximum material condition. 6. 751r-01 obsolete, new standard 751r-02. j m 14 pl pin 1 i.d. 8 1 16 9 top side 0.10 (0.004) t 16 exposed pad 18 back side l h dim a min max min max inches 10.15 10.45 0.400 0.411 millimeters b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc h 3.45 3.66 0.136 0.144 j 0.25 0.32 0.010 0.012 k 0.00 0.10 0.000 0.004 l 4.72 4.93 0.186 0.194 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 a b 9 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.350 0.175 0.050 0.376 0.188 0.200 0.074 dimensions: inches 0.024 0.150 exposed pad c l c l
ncp3163, ncv3163 http://onsemi.com 20 package dimensions dfn18 case 505 ? 01 issue d c 0.15 e2 d2 l b 18x a d notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal 4. coplanarity applies to the exposed pad as well as the terminals. e c e a b dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 6.00 bsc d2 3.98 4.28 e 5.00 bsc e2 2.98 3.28 e 0.50 bsc k 0.20 ??? l 0.45 0.65 c 0.15 pin 1 location a1 (a3) seating plane c 0.08 c 0.10 18x k 18x a 0.10 b c 0.05 c note 3 19 10 18 2x 2x 18x side view top view bottom view 5.30 18x 3.24 0.75 18x 0.30 4.19 pitch dimensions: millimeters 0.50 1 soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncp3163/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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